“CMOS Analog RF IC design using CADANCE EDA”

Objectives

To train the students in:

Analog circuit design.

Do the analysis viz., Transient, Gain, S Parameter, Noise Figure

Generate the layout for analog circuits.

Do the system integration for fabrication

Duration	14 Hours
Timings	Jan 11 & 12, 2018 – 9AM to 5PM

Fees per candidate	1.Internal : Rs.200/-(Including GST)
Eligibility	III year Students from circuit stream
Participants count	30 Nos

Dr.K.N.Vijeyakumar ,
Associate Professor / ECE,
Mr.B.Pradeep Kumar ,
Ms.S.Kalaiselvi,
Mr.H.Maheshkumar, AP/ECE.