Affiliated to Anna University Chennai, Tamil nadu, India.Approved by AICTE.

Archives: ASIC CENTRE OF EXCELLENCE

Centre for Competence in

Custom IC  & Reconfigurable FPGA designs

 

Dr. Mahalingam College of Engineering and Technology (MCET) has established  ASIC Centre of Excellence in Collaboration with Cadence Design Systems, Ireland,  who are market leaders in Electronic Design Automation with the primary objective of imparting skill set to students in custom IC and Reconfigurable FPGA designs on par with present semiconductor industry needs.

 

Objectives  of the partnership

 

1.Opportunity to engage with the Industry on a regular basis to understand their needs  and constantly upgrade the hands-on training offered in Physical Design using Cadence EDA Suite and Reconfigurable FPGA design for signal and image processing applications.

2.Opportunity to upgrade the infrastructure in VLSI and Embedded System Design relevant to semiconductor industry needs.

3.Opportunity to collaborate with the industry for research programs, projects and student internships in the above fields.

4.To offer Faculty Development Programs(FDPs), hands-on training and workshops in Custom IC and Reconfigurable VLSI architecture designs for teaching staff and students. 

FACILITIES:

ASIC Centre of Excellence is passionate in closing the skills and knowledge gaps of today’s Electronics engineers by offering hands-on training in custom IC design in the field of analog, digital and mixed signal disciplines, and Design of Embedded systems,  implementations of Signal and Image Processing architectures using  Reconfigurable FPGAs. The Centre has to its credit the following facilities.

 

a)State-of-the-art CADENCE EDA suite with 20 user license comprising.

 

            CADENCE VIRTUOSO design environment –  For schematic  entry.

            CANDENCE IES   – For digital and mixed signal verification.

            CADENCE ENCOUNTER  –  For physical design of digital and mixed signal

                                                                  circuits.

            CADENCE ASSURA  –  DRC, LVS & Parasitic extraction of analog & Mixed

                                                          signal designs.

            CADENCE SPECTRE  –  Simulation, analysis & parameter estimation of

                                                           schematic  and physical designs.

             CADENCE ALLEGRO – PCB design solution.

 

b)Xilinx Vivado System edition 14.7 with 25 user license and  Zynq-7000 series FPGA boards.

Value Added Courses, Workshops, Hands-On Training, One Credit Courses and Placement Trainings are offered in the following modules.

Module 1 : Custom Analog IC Design Course Duration
1.a. Schematic Entry and Simulation 30 Hrs
CMOS realization of logic expressions, transistor sizing
Introduction to ASIC design flow
Schematic Design using Cadence Virtuoso  -64 design environment
Schematic/Pre- layout Simulation
Parameter Estimation Using Cadence Spectre
1.b.Physical design, RC Extraction and Parameter Estimation
Physical Design of CMOS Circuits using Cadence Assura
DRC, LVS and RC Extraction Using Cadence Assura
Physical design/Post Layout Simulation
Parameter Estimation Using Cadence Spectre
GDS File generation
Module 2 : Custom Digital IC Design
2.a.Design Entry and Verification 30 Hrs
Introduction to Digital Design Flow
Digital Circuit Design using VHDL & Verilog
Design entry and synthesis using Cadence Encounter – RTL Compiler
Simulation and Timing analysis using Cadence IES
2.b.Physical Design, Logic Simulation and Parameter Estimation
Settling time and hold time in sequential system design
Clock Tree Synthesis (CTS) , Constraint file generation
Post CTS Simulation and Synthesis
Physical design and Parameter Estimation of digital circuits using Cadence Encounter –Digital Implementation
GDS file generation

 

Value Added Courses:

Date(s) VAE Course Name No. of Students Attended
30.11.2015 to 04.12.2015 Custom Analog IC design using CADENCE EDA tool 12
20.01.2016 to 25.01.2016 Custom Analog IC design using CADENCE EDA tool 22
18.02.216 to 22.02.2016 Custom Analog IC design using CADENCE EDA tool 21

Workshops Organized:

Academic Year: 2014-2015

 

Date(s) Type of Programme Title No. of Participantsattended Total Resource Persons
External Internal
05.06.2014&06.06.2014 Training Programme For Faculties IC Design Using Cadence EDA Suite 30 30 Technical staffCadence design Systems(India), Bangalore.
05.01.2015 &10.01.2015 Short Term Training Programme Custom Analog IC design using Cadence EDA Suite 11 11 Dr.K.N.VijeyakumarAsso. Prof/EEEMs.K.Saranya & Ms.M.Sangeetha,

APs/EEE

18.02.2015&19.02.2015 Workshop Custom Analog IC Design Using CADENCE EDA Suite 20 20 Dr.K.N.VijeyakumarAsso. Prof/EEEMs.K.Saranya & Ms.M.Sangeetha,

APs/EEE

12.03.2015 Workshop( EEE Association) CMOS Design Flow Using Microwind 30 30 Dr.K.N.VijeyakumarAsso. Prof/EEEMs.K.Saranya & Ms.M.Sangeetha,

APs/EEE

14.03.2015 Workshop(Uddeshah’15) Custom Analog IC Design using CADENCE EDA Suite 24 24 Dr.K.N.VijeyakumarAsso. Prof/EEEMs.K.Saranya&Ms.M.Sangeetha,

AP/EEE

10.04.2015&11.04.2015 Workshop System design using FPGA and Cadence EDA Tools 44 44 Dr.K.N.VijeyakumarAsso. Prof/EEEMs.K.Saranya&Ms.M.Sangeetha,

AP/EEE

 

Academic Year: 2015-2016

 

Date(s) Type of Programme Title No. of Participantsattended Total Resource Persons
External Internal
08.07.2015 &09.07.2015 Workshop Custom Digital IC Design Using CADENCE EDA Suite 10 12 22 Dr.K.N.VijeyakumarAsso. Prof/EEEMs.K.Saranya & Ms.M.Sangeetha,

AP/EEE

Ms.S.Kalaiselvi,

AP/ECE

28.09.2015 Workshop Custom IC design using CADENCE EDA tool 23 9 32 Dr.K.N.VijeyakumarAsso. Prof/EEEMs.K.Saranya&Ms.M.Sangeetha,

AP/EEE

Ms.S.Kalaiselvi,

AP /ECE

08.10.2015 Hands on Training( EEE Association) Custom Analog IC Design using CADENCE EDA Suite 33 33 Dr.K.N.VijeyakumarAsso. Prof/EEEMs.K.Saranya&Ms.M.Sangeetha,

AP/EEE

27.01.2016 & 28.01.2016 Workshop System Design  Using Xilinx Vivado Design Suite on Zynq 7000 SoC Kit 4 28 32 Mr.PrakashCoreEL Technologies, Bangalore
27.02.2016 Workshop( IEEE) Custom Analog IC Design using CADENCE EDA Suite 22 22 Dr.K.N.VijeyakumarAsso. Prof/EEEMs.K.Saranya & Ms.M.Sangeetha,

APs/EEE

Ms.S.Kalaiselvi,

AP /ECE

12.03.2016 Workshop(Uddesha ’16) Custom IC Design using CADENCE EDA Suite 27 27 Dr.K.N.VijeyakumarAsso. Prof/EEEMs.K.Saranya & Ms.M.Sangeetha,

APs/EEE

Ms.S.Kalaiselvi,

AP /ECE

One Credit Courses:

Academic Year OCC Name Dept/Year No. of Students Attended
2015 – 2016 (Even) Custom Analog IC design using CADENCE EDA tool EEE / II 31
Custom Digital IC design using CADENCE EDA tool EEE,E&I,ICE / III 36
2015 – 2016 (Odd) Custom Analog IC design using CADENCE EDA tool M.E (A.E &Com.Sys) / II 24
PCB Design using Cadence EDA Tool EEE,ECE, E&I,ICE / II 30
2014 – 2015 (Even) Custom Analog IC design using CADENCE EDA tool M.E (A.E &Com.Sys) / II 34
2014 – 2015 (Odd) PCB Design using Cadence EDA Tool EEE / II 42

Placement  Achievements:

The circuit stream students of MCET trained  in Custom IC design got placed at Intel India Ltd., Bangalore  during the academic year 2015-16.

Support Activities   

In addition, hands-on training in custom IC design and System design using  Reconfigurable FPGAs are provided to students, Research scholars and industrial experts from  other Engineering Institutions.

Research Activities:

Under Graduate Projects:

Academic Year: 2015 -2016

  1. ASIC Implementation of High Speed Hybrid Full Adder
  2. ASIC Implementation of High Speed Flash ADC Using 180nm CMOS Technology
  3. ASIC design of Low Power High Speed 6T SRAM Using 180nm CMOS Technology
  4. VLSI design of 4×4 Vedic Multiplier using GDI Logic
  5. ASIC Implementation of Low Power Energy Efficient Reversible BCD Adder
  6. ASIC Implementation of Low Power Reversible Comparator
  7. ASIC Implementation of High Performance Error Tolerant adder
  8. Design of Low voltage high performance hybrid full adder
  9. FPGA implementation of Switched Median Filter for Digital Image Processing
  10. VLSI implementation of Mid Point Filter for Digital Image Processing Applications
  11. ASIC design of Energy Efficient Reversible 8 bit Counter

Post Graduate Projects:

Academic Year: 2014 -2015

  1. VLSI implementation of Area Efficient FIR filter for Signal Processing

Applications

  1. ASIC implementation of High Speed Area Efficient Arithmetic Unit Using Vedic

Mathematics

  1. VLSI implementation of high speed carry look ahead adder using cross carry

Logic

Academic Year: 2015 -2016

  1. ASIC Implementation of Binary Arithmetic Unit
  2. ASIC Implementation of Binary Floating Point Unit
  3. ASIC Implementation of Decimal Data path Elements
  4. ASIC Implementation of Radix 10 Decimal Multiplier
  5. ASIC Design of Reversible Arithmetic Unit
  6. Design of an Efficient dual mode architecture for discrete cosine transform

International Journal

Suruthi V and Vijeyakumar K.N, “Design of Area Efficient Truncated Multiplier”International Journal of Electrical and Electronics Engineers, Vol.10, No.5, 2015.
Kalaiselvi S and Vijeyakumar K.N“VLSI implementation of High Speed Area Efficient Arithmetic Unit Using Vedic Mathematics ICTACT Journal of Micro Electronics, 2015.

 

National Conferences

M.Sangeetha, C.Balavenkateshwaran,D.NagaArjun , N.DhivyaPerformance Comparison of Analog to Digital Converter in 180nm CMOS Technologyin National Conference on Communication , Computing and Networks – NCCCN 2016, Bannari Amman Institute of Technology, Sathy.
M.Subhadevi , K.N.Vijeya Kumar, S.Kalaiselvi , M.SangeethaComparison of High Performance Arithmetic Units in 180nm CMOS Technology” in National Conference on Communication , Computing and Networks – NCCCN 2016, Bannari Amman Institute of Technology, Sathy.
R.Nandhinipriya , R.Dhivya, M.Subhadevi“Comparison of High Speed Adders in CMOS Technologyin National Conference on Communication , Computing and Networks – NCCCN 2016, Bannari Amman Institute of Technology, Sathy.
L.Priyanka, K.Saranya, J.S.ShinyComparison of High Performance Radix-X Decimal Multipliersin National Conference on Communication, Computing and Networks – NCCCN 2016, Bannari Amman Institute of Technology, Sathy.
B.Pavithran, K.N.Vijeyakumar, K.Saranya “Performance Comparison of Reversible Datapath Elementsin National Conference on Communication, Computing and Networks – NCCCN 2016, Bannari Amman Institute of Technology, Sathy.

 

 

Faculty Members

Dr.A.Senthilkumar, Professor & Head/EEE

Dr.K.N.Vijeyakumar, Associate Professor/EEE

Ms.K.Saranya, Assistant Professor/EEE

Ms.M.Sangeetha, Assistant Professor/EEE

Ms.S.Kalaiselvi, Assistant Professor/ECE

 

Contact

Dr.K.N.Vijeyakumar

Associate Professor

Department of Electrical and Electronics Engineering

Dr.Mahalingam College of Engineering and Technology

Pollachi.

Office Ph: 04259-236030/40/50,  Fax:04259-236070

Email: info@mcet.in