ASIC CENTRE OF EXCELLENCE

ASIC CENTRE OF EXCELLENCE

ASIC Centre of Excellence was established in Collaboration with Cadence Design Systems, Ireland in the year 2013, with the primary objective of imparting skill set to students in custom IC and Reconfigurable FPGA designs on par with present semiconductor industry needs.

Objectives  of the partnership

1.Opportunity to engage with the Industry on a regular basis to understand their needs and constantly upgrade the hands-on training offered in Physical Design using Cadence EDA Suite and Reconfigurable FPGA design for signal and image processing applications.

2.Opportunity to upgrade the infrastructure in VLSI and Embedded System Design relevant to semiconductor industry needs.

3.Opportunity to collaborate with the industry for research programs, projects, student internships and IC fabrication.

4.To offer Faculty Development Programs(FDPs), hands-on training and workshops in Custom IC and Reconfigurable VLSI architecture designs for teaching staff and students. 

FACILITIES:

ASIC Centre of Excellence is passionate in closing the skills and knowledge gaps of today’s Electronics engineers by offering hands-on training in custom IC design in the field of analog, digital and mixed signal disciplines, Design of Embedded systems and implementation of Signal and Image Processing architectures using Reconfigurable FPGAs. The Centre has to its credit the following facilities

a)State-of-the-art CADENCE EDA suite with 20 user license comprising.

            CADENCE VIRTUOSO design environment –  For schematic  entry.

            CANDENCE IES   – For digital and mixed signal verification.

            CADENCE ENCOUNTER  –  For physical design of digital and mixed signal

                                                                  circuits.

            CADENCE ASSURA  –  DRC, LVS & Parasitic extraction of analog & Mixed

                                                          signal designs.

            CADENCE SPECTRE  –  Simulation, analysis & parameter estimation of Analog, Radio

                                                           Frequency (RF), and mixed-signal circuits.

             CADENCE ALLEGRO – PCB design solution.

 

b)State-of-the-art MENTOR EDA suite with 10 user license comprising.

            MENTOR PYXIS design environment – For schematic entry.

            MENTOR QUESTA SIM – ELDO   – For digital and mixed signal verification.

             MENTOR NITRO – SOC Design.

            CALIBRE INROUTE  –  For physical design of digital and mixed signal circuits

            MENTOR CALIBRE  –  DRC, LVS & Parasitic extraction of analog & Mixed signal

                                                           designs.

            MENTOR TESSENT  –  Simulation, analysis & parameter estimation of Analog, Radio

                                                           Frequency (RF), and mixed-signal circuits.

             MENTOR XPEDITION – PCB design solution.

             TANNER EDA – For physical design of digital and mixed signal circuits..

 

c)Xilinx Vivado System edition 14.7 with 25 user license and Zynq-7000 series FPGA boards.

 

d)Server Configuration: HP DL350p G8 server, Intel Xeon E5 2609v2 (2.5 Ghz quad core)Processor, 16GB RAM, 2”1TB Hard Disk (Extendable).

Ongoing Doctoral Research

S. No

Scholar Name

Supervisor Name

Title of the Research

1

Ms.K.Saranya

Dr.K.N.Vijeyakumar,

Associate Prof./ECE

ASIC Implementation of Efficient Reversible Arithmetic Processing Unit for Signal Processing and Cryptographic Applications
2

Ms.Gnanmbikai

Design of Efficient VLSI Architecture for Image denoising

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6xr954 Custom Analog and Mixed Signal IC Design
6xr954 Verilog – HDL modeling & FPGA implementation of digital systems
6xr954 System Design and Verification Using System Verilog – HDL
6xr954 FPGA implementation of Image & Signal Processing Algorithms
6xr954 Design and Hardware modeling of fundamental Electronics Circuits

MoU has been signed with

a) Semiconductor Laboratory (Department of Space), Chandigarh for IC fabrication in SCL PDK 180nm Technology.
b) EmbDes Technologies Pvt Ltd., Bangalore
c) Mentor Graphics – Bangalore

Industry Tie up

6xr954 Intel Corporation Pvt Ltd., Bangalore
6xr954 Semiconductor Laboratory (Department of Space), Chandigarh- Delhi
6xr954 Mentor Graphics, Bangalore
6xr954 Cadence Design System, Bangalore
6xr954 EmbDes Technologies, Bangalore
6xr954 Caliber Embedded Technologies, Coimbatore
6xr954 Microsemi Corporation, Bangalore
6xr954 SOCDV Technologies Pvt Ltd., Bangalore
6xr954 CoreEL Technologies Pvt Ltd., Bangalore

Placement Details

S.No.

Company Name

2015-16

2016-17

2017-18

2018-19

01

Intel Corporation Pvt Ltd., Bangalore

3

4

3

2

02

EmbDes Technologies, Bangalore

1

1

03

Mirafra Software Technologies Pvt Ltd., Bangalore

1

04

Test and Verification Solutions, Bangalore

1

05

Audience Communications Systems India , Bangalore

1

06

Caliber Embedded Technologies India (P) Ltd – Coimbatore

3

07

Altran Technologies- Coimbatore

4

Internship Details

S.No.

Company Name

2015-16

2016-17

2017-18

2018-19

01 Intel Corporation Pvt Ltd., Bangalore

2

1

02 Semiconductor Laboratory , Chandigarh

3

3

03 Caliber Embedded Technologies, Coimbatore

9

04 SOCDV Technologies Pvt Ltd., Bangalore

10

Workshops and Value Added programmes on “CMOS Analog & Mixed Signal IC Design” and “FPGA implementation of image and signal processing algorithms” are carried out periodically.

Workshops & Value Added Courses Organized

Workshops & Value Added Courses Organized

Number Of Students Benefitted

Number_  Students Benefitted

Value Added Courses:

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Workshops Organized:

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One Credit Courses

Academic Year :2016-2017

Academic Year

OCC Name

Dept/Year

No. of Students Attended

Handling Faculty

2016-2017 (Odd)

Custom Analog IC design using CADENCE EDA tool

EEE,EIE/II

27

Dr.K.N.Vijeyakumar,Asso. Prof/EEE,Ms.M.Sangeetha, AP/EEE
FPGA Design Using Vivado

EEE,E&I,ICE / III

30

Ms.K.Saranya,Ms.R. Dhivya, AP/EEE

2016-2017 (Even)

Custom Analog IC design using CADENCE EDA tool

M.E (A.E & Com. Sys) / II

16

Dr.K.N.Vijeyakumar,Asso. Prof/EEE,Ms.M.Sangeetha, AP/EEE
Custom Digital IC Design Using  Cadence EDA Tool

EEE / II

27

Ms.K.Saranya,Ms.J.S. Shiny, AP/EEE

Consultancy Works

 S.No

Name of the Work

Industry / Institution

Date

01

Datapath Element Design Sri Ranganathar College of Engineering, Coimbatore 5th Oct 2017

02

Memory Deign SRM University – Chennai 8th & 9th Mar 2018

03

Implementation of Approximate Datapath Elements Knowledge Institute of Technology, Salem

Kalaignar Karunanidhi Institute of Technology, Coimbatore

5th & 6th Oct 2018

04

Implementation of Image Processing Algorithms Ranganthan Engineering College, Coimbatore 3rd Nov 2018

International Journal

Suruthi V and Vijeyakumar K.N, “Design of Area Efficient Truncated Multiplier”International Journal of Electrical and Electronics Engineers, Vol.10, No.5, 2015.
Kalaiselvi S and Vijeyakumar K.N“VLSI implementation of High Speed Area Efficient Arithmetic Unit Using Vedic Mathematics ICTACT Journal of Micro Electronics, 2015.

 

National Conferences

M.Sangeetha, C.Balavenkateshwaran,D.NagaArjun , N.DhivyaPerformance Comparison of Analog to Digital Converter in 180nm CMOS Technologyin National Conference on Communication , Computing and Networks – NCCCN 2016, Bannari Amman Institute of Technology, Sathy.
M.Subhadevi , K.N.Vijeya Kumar, S.Kalaiselvi , M.SangeethaComparison of High Performance Arithmetic Units in 180nm CMOS Technology” in National Conference on Communication , Computing and Networks – NCCCN 2016, Bannari Amman Institute of Technology, Sathy.
R.Nandhinipriya , R.Dhivya, M.Subhadevi“Comparison of High Speed Adders in CMOS Technologyin National Conference on Communication , Computing and Networks – NCCCN 2016, Bannari Amman Institute of Technology, Sathy.
L.Priyanka, K.Saranya, J.S.ShinyComparison of High Performance Radix-X Decimal Multipliersin National Conference on Communication, Computing and Networks – NCCCN 2016, Bannari Amman Institute of Technology, Sathy.
B.Pavithran, K.N.Vijeyakumar, K.Saranya “Performance Comparison of Reversible Datapath Elementsin National Conference on Communication, Computing and Networks – NCCCN 2016, Bannari Amman Institute of Technology, Sathy.

 

 

Faculty Members

Dr.A.Senthilkumar, Professor & Head/EEE

Dr.K.N.Vijeyakumar, Associate Professor/EEE

Ms.K.Saranya, Assistant Professor/EEE

Ms.M.Sangeetha, Assistant Professor/EEE

Ms.S.Kalaiselvi, Assistant Professor/ECE

 

Contact

Dr.K.N.Vijeyakumar

Associate Professor

Department of Electrical and Electronics Engineering

Dr.Mahalingam College of Engineering and Technology

Pollachi.

Office Ph: 04259-236030/40/50,  Fax:04259-236070

Email: info@mcet.in

S.NO Title of the Website URL of Website
1 Semi-Conductor Laboratory http://www.scl.gov.in/
2 TSMC http://www.tsmc.com/english/default.htm
3 Special Man Power Development Programme http://smdp2vlsi.gov.in/smdp2vlsi/index.jsp

Centre Incharge

Dr.K.N.Vijeyakumar M.E, Ph.D.,
Associate Professor/ECE
vijey.tn@drmcet.ac.in

Co-ordinator/ECE

Ms.S.Kalaiselvi
Assistant Professor/ECE
kalaiselvi@drmcet.ac.in

Co-ordinator/EEE

Dr.B.Vinoth Kumar
Assistant Professor/EEE
vinothkumarb@drmcet.ac.in

Staff Members

Dr.C.Kalamani
Assistant Professor(SS)/ECE
kalamec@drmcet.ac.in

Mrs.K.Saranya
Assistant Professor/EEE
saranya@drmcet.ac.in

Workshop on Custom Digital IC Design Using Cadence EDA Suite

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Workshop on CMOS Analog IC Design and Recent trends in Physical Design using Cadence EDA Tool

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VAC on CMOS Digital IC Design Using Cadence EDA Tool

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CMOS Analog IC Design Using Cadence EDA Tool

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Workshop on CMOS Analog RF IC Design Using Cadence EDA Tool

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Workshop on CMOS Analog RF IC Design Using Cadence EDA Tool

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CMOS Analog IC Design Using Cadence EDA Tool

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Workshop on System Design  Using Xilinx Vivado Design

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Digital Design of IC using verilog/VHDL code using xillinx and QuestaSim (Mentor Graphics) tool

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Design and Analysis of Amplifier Circuits using Cadence EDA Tool

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CMOS Analog IC Design Using Cadence EDA Tool

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