ASIC CENTRE OF EXCELLENCE

Centre for Competence in

Custom IC  & Reconfigurable FPGA designs

Dr. Mahalingam College of Engineering and Technology (MCET) has established  ASIC Centre of Excellence in Collaboration with Cadence Design Systems, Ireland,  who are market leaders in Electronic Design Automation with the primary objective of imparting skill set to students in custom IC and Reconfigurable FPGA designs on par with present semiconductor industry needs.

Objectives  of the partnership

1.Opportunity to engage with the Industry on a regular basis to understand their needs  and constantly upgrade the hands-on training offered in Physical Design using Cadence EDA Suite and Reconfigurable FPGA design for signal and image processing applications.

2.Opportunity to upgrade the infrastructure in VLSI and Embedded System Design relevant to semiconductor industry needs.

3.Opportunity to collaborate with the industry for research programs, projects and student internships in the above fields.

4.To offer Faculty Development Programs(FDPs), hands-on training and workshops in Custom IC and Reconfigurable VLSI architecture designs for teaching staff and students. 

FACILITIES:

ASIC Centre of Excellence is passionate in closing the skills and knowledge gaps of today’s Electronics engineers by offering hands-on training in custom IC design in the field of analog, digital and mixed signal disciplines, and Design of Embedded systems,  implementations of Signal and Image Processing architectures using  Reconfigurable FPGAs. The Centre has to its credit the following facilities.

 

a)State-of-the-art CADENCE EDA suite with 20 user license comprising.

 

            CADENCE VIRTUOSO design environment –  For schematic  entry.

            CANDENCE IES   – For digital and mixed signal verification.

            CADENCE ENCOUNTER  –  For physical design of digital and mixed signal

                                                                  circuits.

            CADENCE ASSURA  –  DRC, LVS & Parasitic extraction of analog & Mixed

                                                          signal designs.

            CADENCE SPECTRE  –  Simulation, analysis & parameter estimation of Analog, Radio

                                                           Frequency (RF), and mixed-signal circuits.

             CADENCE ALLEGRO – PCB design solution.

 

b)Xilinx Vivado System edition 14.7 with 25 user license and  Zynq-7000 series FPGA boards.

c)Server Configuration: HP DL350p G8 server, Intel Xeon E5 2609v2 (2.5 Ghz quad core)Processor,16GB RAM, 2”1TB Hard Disk (Extendable).

Ongoing Doctoral Research

S. No

Scholar Name

Supervisor Name

Title of the Research

1

Mr.A.Nandhakumar

Dr.A.Senthilkumar,
Professor/EEE

VLSI  Implementation of  Video
Processing  Architecture

2

Ms.K.Saranya

Dr.K.N.Vijeyakumar,
Associate Prof./ECE

ASIC Implementation of Efficient Reversible Arithmetic Processing Unit for Signal Processing and Cryptographic Applications

3

Ms.Gnanmbikai Design of Efficient VLSI Architecture for Image denoising

down arrow   Academic Year: 2017-2018 :  Download / View

down arrow   Academic Year: 2016-2017 :  Download / View

down arrow   Academic Year: 2015-2016 :  Download / View

Value Added Courses, Workshops, Hands-On Training, One Credit Courses and Placement Trainings are offered in the following modules.

Module 1 : Custom Analog IC Design Course Duration
1.a. Schematic Entry and Simulation 30 Hrs
CMOS realization of logic expressions, transistor sizing
Introduction to ASIC design flow
Schematic Design using Cadence Virtuoso  -64 design environment
Schematic/Pre- layout Simulation
Parameter Estimation Using Cadence Spectre
1.b.Physical design, RC Extraction and Parameter Estimation
Physical Design of CMOS Circuits using Cadence Assura
DRC, LVS and RC Extraction Using Cadence Assura
Physical design/Post Layout Simulation
Parameter Estimation Using Cadence Spectre
GDS File generation
Module 2 : Custom Digital IC Design
2.a.Design Entry and Verification 30 Hrs
Introduction to Digital Design Flow
Digital Circuit Design using VHDL & Verilog
Design entry and synthesis using Cadence Encounter – RTL Compiler
Simulation and Timing analysis using Cadence IES
2.b.Physical Design, Logic Simulation and Parameter Estimation
Settling time and hold time in sequential system design
Clock Tree Synthesis (CTS) , Constraint file generation
Post CTS Simulation and Synthesis
Physical design and Parameter Estimation of digital circuits using Cadence Encounter –Digital Implementation
GDS file generation

 

Value Added Courses:

down arrow   Value Added Courses: 2016-2017 :   Download / View

down arrow   Value Added Courses: 2015-2016 :  Download / View

Workshops Organized:

down arrow   Academic Year: 2016-2017 :  Download / View

down arrow   Academic Year: 2015-2016 :   Download / View

down arrow   Academic Year: 2014-2015 :   Download / View

One Credit Courses

Academic Year :2016-2017

Academic Year

OCC Name

Dept/Year

No. of Students Attended

Handling Faculty

2016-2017 (Odd)

Custom Analog IC design using CADENCE EDA tool

EEE,EIE/II

27

Dr.K.N.Vijeyakumar,Asso. Prof/EEE,Ms.M.Sangeetha, AP/EEE
FPGA Design Using Vivado

EEE,E&I,ICE / III

30

Ms.K.Saranya,Ms.R. Dhivya, AP/EEE

2016-2017 (Even)

Custom Analog IC design using CADENCE EDA tool

M.E (A.E & Com. Sys) / II

16

Dr.K.N.Vijeyakumar,Asso. Prof/EEE,Ms.M.Sangeetha, AP/EEE
Custom Digital IC Design Using  Cadence EDA Tool

EEE / II

27

Ms.K.Saranya,Ms.J.S. Shiny, AP/EEE
Academic Year OCC Name Dept/Year No. of Students Attended
2015 – 2016 (Even) Custom Analog IC design using CADENCE EDA tool EEE / II 31
Custom Digital IC design using CADENCE EDA tool EEE,E&I,ICE / III 36
2015 – 2016 (Odd) Custom Analog IC design using CADENCE EDA tool M.E (A.E &Com.Sys) / II 24
PCB Design using Cadence EDA Tool EEE,ECE, E&I,ICE / II 30
2014 – 2015 (Even) Custom Analog IC design using CADENCE EDA tool M.E (A.E &Com.Sys) / II 34
2014 – 2015 (Odd) PCB Design using Cadence EDA Tool EEE / II 42

Placement  Achievements:

The circuit stream students of MCET trained  in Custom IC design got placed at Intel India Ltd., Bangalore  during the academic year 2015-16.

Support Activities   

In addition, hands-on training in custom IC design and System design using  Reconfigurable FPGAs are provided to students, Research scholars and industrial experts from  other Engineering Institutions.

Research Activities

Under Graduate Projects:

Academic Year: 2015 -2016

ASIC Implementation of High Speed Hybrid Full Adder
ASIC Implementation of High Speed Flash ADC Using 180nm CMOS Technology
ASIC design of Low Power High Speed 6T SRAM Using 180nm CMOS Technology
VLSI design of 4×4 Vedic Multiplier using GDI Logic
ASIC Implementation of Low Power Energy Efficient Reversible BCD Adder
ASIC Implementation of Low Power Reversible Comparator
ASIC Implementation of High Performance Error Tolerant adder
Design of Low voltage high performance hybrid full adder
FPGA implementation of Switched Median Filter for Digital Image Processing
VLSI implementation of Mid Point Filter for Digital Image Processing Applications
ASIC design of Energy Efficient Reversible 8 bit Counter

Post Graduate Projects:

Academic Year: 2014 -2015

VLSI implementation of Area Efficient FIR filter for Signal Processing Applications
ASIC implementation of High Speed Area Efficient Arithmetic Unit Using Vedic Mathematics
VLSI implementation of high speed carry look ahead adder using cross carry Logic

Academic Year: 2015 -2016

ASIC Implementation of Binary Arithmetic Unit
ASIC Implementation of Binary Floating Point Unit
ASIC Implementation of Decimal Data path Elements
ASIC Implementation of Radix 10 Decimal Multiplier
ASIC Design of Reversible Arithmetic Unit
Design of an Efficient dual mode architecture for discrete cosine transform

International Journal

Suruthi V and Vijeyakumar K.N, “Design of Area Efficient Truncated Multiplier”International Journal of Electrical and Electronics Engineers, Vol.10, No.5, 2015.
Kalaiselvi S and Vijeyakumar K.N“VLSI implementation of High Speed Area Efficient Arithmetic Unit Using Vedic Mathematics ICTACT Journal of Micro Electronics, 2015.

 

National Conferences

M.Sangeetha, C.Balavenkateshwaran,D.NagaArjun , N.DhivyaPerformance Comparison of Analog to Digital Converter in 180nm CMOS Technologyin National Conference on Communication , Computing and Networks – NCCCN 2016, Bannari Amman Institute of Technology, Sathy.
M.Subhadevi , K.N.Vijeya Kumar, S.Kalaiselvi , M.SangeethaComparison of High Performance Arithmetic Units in 180nm CMOS Technology” in National Conference on Communication , Computing and Networks – NCCCN 2016, Bannari Amman Institute of Technology, Sathy.
R.Nandhinipriya , R.Dhivya, M.Subhadevi“Comparison of High Speed Adders in CMOS Technologyin National Conference on Communication , Computing and Networks – NCCCN 2016, Bannari Amman Institute of Technology, Sathy.
L.Priyanka, K.Saranya, J.S.ShinyComparison of High Performance Radix-X Decimal Multipliersin National Conference on Communication, Computing and Networks – NCCCN 2016, Bannari Amman Institute of Technology, Sathy.
B.Pavithran, K.N.Vijeyakumar, K.Saranya “Performance Comparison of Reversible Datapath Elementsin National Conference on Communication, Computing and Networks – NCCCN 2016, Bannari Amman Institute of Technology, Sathy.

 

 

Faculty Members

Dr.A.Senthilkumar, Professor & Head/EEE

Dr.K.N.Vijeyakumar, Associate Professor/EEE

Ms.K.Saranya, Assistant Professor/EEE

Ms.M.Sangeetha, Assistant Professor/EEE

Ms.S.Kalaiselvi, Assistant Professor/ECE

 

Contact

Dr.K.N.Vijeyakumar

Associate Professor

Department of Electrical and Electronics Engineering

Dr.Mahalingam College of Engineering and Technology

Pollachi.

Office Ph: 04259-236030/40/50,  Fax:04259-236070

Email: info@mcet.in

S.NO Title of the Website URL of Website
1 Semi-Conductor Laboratory http://www.scl.gov.in/
2 TSMC http://www.tsmc.com/english/default.htm
3 Special Man Power Development Programme http://smdp2vlsi.gov.in/smdp2vlsi/index.jsp

Centre Incharge

Dr.K.N.Vijeyakumar M.E, Ph.D.,
Associate Professor/ECE

Co-ordinator/ECE

Ms.S.Kalaiselvi
Assistant Professor/ECE

Co-ordinator/EEE

Ms.M.Sangeetha
Assistant Professor/EEE

Staff Members

Dr.B.Vinoth Kumar
Assistant Professor/EEE

Mrs.Kalamani
Assistant Professor/ECE

Mrs.K.Saranya
Assistant Professor/EEE

Workshop on Custom Digital IC Design Using Cadence EDA Suite

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Workshop on CMOS Analog IC Design and Recent trends in Physical Design using Cadence EDA Tool

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VAC on CMOS Digital IC Design Using Cadence EDA Tool

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CMOS Analog IC Design Using Cadence EDA Tool

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Workshop on CMOS Analog RF IC Design Using Cadence EDA Tool

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Workshop on CMOS Analog RF IC Design Using Cadence EDA Tool

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CMOS Analog IC Design Using Cadence EDA Tool

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Workshop on System Design  Using Xilinx Vivado Design

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Digital Design of IC using verilog/VHDL code using xillinx and QuestaSim (Mentor Graphics) tool

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Design and Analysis of Amplifier Circuits using Cadence EDA Tool

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CMOS Analog IC Design Using Cadence EDA Tool

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