CMOS Analog RF IC design using CADANCE EDA

“CMOS Analog RF IC design using CADANCE EDA”

Objectives

To train the students in:

down arrow Analog circuit design.

down arrow Do the analysis viz., Transient, Gain, S Parameter, Noise Figure

down arrow Generate the layout for analog circuits.

down arrow Do the system integration for fabrication

Duration & Timings

Duration

14 Hours

Timings

Jan 11 & 12, 2018 – 9AM to 5PM

Conditions

Fees per candidate

1.Internal : Rs.200/-(Including GST)

Eligibility

III year Students from circuit stream

Participants count

30 Nos

Course Coordinators

Dr.K.N.Vijeyakumar ,
Associate Professor / ECE,
Mr.B.Pradeep Kumar ,
Ms.S.Kalaiselvi,
Mr.H.Maheshkumar, AP/ECE.

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